Realization of Aging-Aware Reliable Multiplier Design using Verilog HDL

Authors:SUPRIYA JULUGANTI, T. MUNI REDDY

0403-0408

Realization of Power Optimized LFSR for Testing Applications

Authors:CHANDANA G, NARSAPPA REDDY, MIRZA SAJID ALI BAIG

0409-0413

Performance and Evolution of Delay Efficient Carry Select Adder using Dlatch

Authors:SANDU RAJASEKHAR, ESLAVATH RAMAKRISHNA

0414-0420

Implementation of Area Optimized Video Transform Engine by using STS Strategy

Authors:CHAITANYA ABBAGANI, NARSAPPA REDDY, MIRZA SAJID ALI BAIG

0421-0425

Implementation of Testable Sequential Circuits using on Reversible Logic Gates

Authors:SWETHA BYRAM, MIRZA SAJID ALI BAIG, NARSAPPA REDDY

0426-0430

Design of Data Encoding Techniques for Reducing Energy Consumption in Network-On-Chip

Authors:K. RAMESH, D. KHALANDAR BASHA

0431-0439

Design and Implementation of Bit-Level Implementation for Efficient FIR Filter Based On Optimization of Adder-Trees

Authors:B. NAGARJUN SINGH, APARNA

0440-0444

A Fast Binary to BCD Conversion for Binary/Decimal Multi-Operand Adder

Authors:M. SHIRISHA, M. CHANDRASHEKHAR

0445-0447

Network-On-Chip Implementation for Data Encoding Techniques using Reducing Energy Consumption

Authors:M. VENU, T. OOHA, B. NAGARJUN SINGH

0448-0454

BIST to Diagnosis Delay Fault in the LUT of Cluster Based FPGA

Authors:D. MOUNIKA, SYED AZHARUDDIN

0455-0460